A hardware/software codesign method for a general purpose reconfigurable co-processor

Author

Kimura, Shinji ; Yukishita, Mitsuteru ; Itou, Yasufumi ; Nagoya, Akira ; Hirao, Makoto ; Watanabe, Katumasa

Author_Institution

Nara Inst. of Sci. & Technol., Japan

fYear

1997

fDate

24-26 Mar 1997

Firstpage

147

Lastpage

151

Abstract

Shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGAs, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via DMA-based memory sharing. We also show co-operation examples and the effectiveness of our approach for the fast execution of user processes

Keywords

cache storage; coprocessors; field programmable gate arrays; general purpose computers; high level synthesis; reconfigurable architectures; shared memory systems; software engineering; DMA-based memory sharing; FPGA; control part; cooperation method; coprocessor architecture; direct memory access; fast user process execution; general-purpose reconfigurable coprocessor; hardware/software codesign method; hardware/software separation method; internal cache; system bus; Clocks; Communications technology; Computer architecture; Coprocessors; Field programmable gate arrays; Hardware; Laboratories; Programmable logic arrays; Read-write memory; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware/Software Codesign, 1997. (CODES/CASHE '97), Proceedings of the Fifth International Workshop on

Conference_Location

Braunschweig

ISSN

1092-6100

Print_ISBN

0-8186-7895-X

Type

conf

DOI

10.1109/HSC.1997.584594

Filename

584594