The Alpha 21264: a 500 MHz out-of-order execution microprocessor

Author

Leibholz, D. ; Razdan, R.

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1997

fDate

23-26 Feb. 1997

Firstpage

28

Lastpage

36

Abstract

The paper describes the internal organization of the 21264, a 500 MHz, out of order, quad fetch, six way issue microprocessor. The aggressive cycle time of the 21264 in combination with many architectural innovations, such as out of order and speculative execution, enable this microprocessor to deliver an estimated 30 SpecInt95 and 50 SpecFp95 performance. In addition, the 21264 can sustain 5+ Gigabytes/sec of bandwidth to an L2 cache and 3+ Gigabytes/sec to memory for high performance on memory-intensive applications.

Keywords

CMOS integrated circuits; computer architecture; microprocessor chips; 30 SpecInt95; 5 Gbyte/s; 50 SpecFp95 performance; 500 mHz; Alpha 21264 microprocessor; L2 cache; aggressive cycle time; architectural innovations; bandwidth; internal organization; memory-intensive applications; out of order execution microprocessor; six way issue microprocessor; speculative execution; Acceleration; Bandwidth; Circuits; Computer architecture; Delay; Microprocessors; Motion estimation; Out of order; Registers; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon '97. Proceedings, IEEE

Conference_Location

San Jose, CA, USA

ISSN

1063-6390

Print_ISBN

0-8186-7804-6

Type

conf

DOI

10.1109/CMPCON.1997.584667

Filename

584667