Reconfigurable systolic Viterbi decoder

This paper introduces a new algorithm which saves the power consumption of the systolic Viterbi decoder. The new algorithm dynamically changes the truncated path length of a Viterbi decoder according to the channel condition, resulting in reduction of power consumption. This algorithm is based on the observation that the truncated path length and bit error rate are closely related. If we set the truncated path length short, we can reduce the size of the decoder even though the system performance is sacrificed. We propose a reconfiguration of the truncated path length according to channel state. It is shown that power consumption of a systolic Viterbi decoder with convolutional code for a constraint length K=3 and a code rate R=1/2 can be eliminated over 20 percent at the bit error rate of 10^-3 in a Rayleigh fading channel. Furthermore, the longer the truncated path length becomes, the more effective the proposed method is