Title :
A comprehensive diagnostics software strategy for IDT´s microprocessors
Author_Institution :
Integrated Device Technol. Inc., Santa Clara, CA, USA
Abstract :
Although it is routine to write tests that verify the basic functions of the cache or pipeline, how often is verification of a write-after-write interlock operation or an interrupt leading to an aborted cache flush cycle operation performed? Diagnostic software verifies the architectural compliance and functionality of a microprocessor design and is one of the most important areas to consider during the hardware development phase. A design is only as good as the diagnostics that test and verify it. But IDT is highly aware of the importance of diagnostics software, and a diagnostics team was formed to design a world class functional test suite for its microprocessors. The goal of this team was to create structured, modular, and highly leverageable tests that conformed to a vertical diagnostics strategy, designed to address complex operation sequences such as pipeline interlocks and hazards as well as asynchronous interruptions to the pipeline, in various combinations. To simplify the debugging efforts of logic designers, a generic exception handler capable of handling nested interrupts and exceptions-in the correct priority order to accommodate simultaneous exception occurrences-was implemented. To cover all possible processor cycle combinations and to include the areas that controlled diagnostics can not reach, pseudo-random diagnostics code was generated. To further guarantee a comprehensive diagnostics strategy, several application programs written in C were developed.
Keywords :
computer testing; exception handling; integrated circuit testing; interrupts; pipeline processing; program diagnostics; IDT microprocessors; aborted cache flush cycle operation; architectural compliance; asynchronous interruptions; complex operation sequences; comprehensive diagnostics software strategy; debugging efforts; generic exception handler; hardware development phase; highly leverageable tests; logic designers; microprocessor design; nested interrupts; pipeline interlocks; processor cycle combinations; pseudo-random diagnostics code; simultaneous exception occurrences; vertical diagnostics strategy; world class functional test suite; write-after-write interlock operation; Arithmetic; Debugging; Hardware; Hazards; Logic design; Logic testing; Microprocessors; Pipelines; Software testing; Stress;
Conference_Titel :
Compcon '97. Proceedings, IEEE
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7804-6
DOI :
10.1109/CMPCON.1997.584681