A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion

The DTG discussed in this paper, reduces data-dependent jitter (DDJ) and offers ns-order delay span for input data rates of up to 11Gb/s. The fine-delay blocks consist of 6 sub-blocks. Total fine delay is adjusted by combining the delays of the 6 sub-blocks using the control inputs for the fine-delay block. NMOS transistors are used as the variable capacitors (VCs) for delay control, because they provide small capacitance of <50fF that makes it possible to generate sub- ps delay. Since the DTG uses a spectrum-conversion technique that suppresses the effect of the group-delay deviation of the delay gates, its output jitter is reduced to one-third that of a conventional DTG