A digital phase-locked loop with a low frequency clock

A DPLL (digital phase-locked-loop) with a novel digital VCO (voltage controlled oscillator), which uses the direct frequency synthesis technique and frequency control, has been proposed and analyzed theoretically and by experiments. The relationship between the clock frequency and the performance of the loop has been examined. It has been shown that a good phase-lock precision is obtained if the clock component is removed from the output signal by the smoothing filter. Results for low-frequency clock operation of the DPLL suggest that it could be used for high-frequency applications. The steady-state characteristics and the dynamic response of the system are compared with those of the conventional system. Due to the sensitivity of the binary phase frequency detector and frequency control, its performance in the presence of high noise levels can be inferior to that of the conventional system, but the locking range and the frequency acquisition performance are significantly improved