Title :
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure
Author :
Park, Ki-Tae ; Kim, Doogon ; Hwang, Soonwook ; Kang, Myounggon ; Cho, Hoosung ; Jeong, Youngwook ; Seo, Yong-Il ; Jang, Jaehoon ; Kim, Han-Soo ; Jung, Soon-Moon ; Lee, Yeong-Taek ; Kim, Changhyun ; Lee, Won-Seong
Author_Institution :
Samsung, Hwasung
Abstract :
Recently, 3-dimensional (3D) memories have regained attention as a potential future memory solution featuring low cost, high density and high performance. We present a 3D double stacked 4Gb MLC NAND flash memory device with shared bitline structure, with a cell size of 0.0021mum2/bit per unit feature area. The device is designed to support 3D stacking and fabricated by S3 and 45nm floating-gate CMOS technologies.
Keywords :
CMOS memory circuits; NAND circuits; flash memories; 3D multilevel NAND flash memory; 3D stacking; CMOS technology; memory size 4 GByte; shared bitline structure; size 45 nm; Circuits; Clocks; Costs; Degradation; Interference; Nonvolatile memory; Random access memory; Stacking; Very large scale integration; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523281
