Title :
A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS
Author :
Hsueh, Kang-Wei ; Chou, Yu-Kai ; Tu, Yu-Hsuan ; Chen, Yi-Fu ; Yang, Ya-Lun ; Li, Hung-Sung
Author_Institution :
MediaTek, Hsinchu
Abstract :
This paper demonstrates a IV 200MS/s pipelined ADC with digital background calibration in 65nm digital CMOS process.
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital integrated circuits; low-power electronics; pipeline arithmetic; digital CMOS process; digital background calibration; pipelined ADC; voltage 1 V; CMOS process; Calibration; Capacitors; Convergence; Costs; Fluctuations; Semiconductor device measurement; Signal processing; Silicon; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523299
