DocumentCode
3469002
Title
Exploring the temporal placement for partially reconfigurable device
Author
Ayadi, Rajaa ; Ouni, B. ; Mtibaa, Abdellatif
Author_Institution
Lab. d´Electron. et de Microelectron. (Lab. IT06), Fac. des Sci. de Monastir, Monastir, Tunisia
fYear
2011
fDate
3-5 March 2011
Firstpage
1
Lastpage
4
Abstract
In this paper, we examine the temporal placement, showing how it can be decomposed into a number of distinct but not independent subtasks. Then, we detail the early algorithms that have been developed for solving the temporal placement problem. Next we introduced a new temporal placement algorithm that aims to reduce the routing cast between modules. And finally, experiments are conducted in order to evaluate the complexity and design performances of the proposed algorithm versus others temporal placement algorithms.
Keywords
electronic design automation; field programmable gate arrays; integrated circuit layout; FPGA; partially reconfigurable device; temporal placement algorithm; temporal placement problem; Transform coding; FPGA; partially reconfigurable systems; temporal placement;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computing and Control Applications (CCCA), 2011 International Conference on
Conference_Location
Hammamet
Print_ISBN
978-1-4244-9795-9
Type
conf
DOI
10.1109/CCCA.2011.6031482
Filename
6031482
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