DocumentCode
3469303
Title
A design of high speed AGTL+ output buffer
Author
Wang, Donglin ; Li, Shaoqing ; Zhao, Zhenyu
Author_Institution
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha
Volume
2
fYear
2005
fDate
24-0 Oct. 2005
Firstpage
616
Lastpage
619
Abstract
AGTL+ (assisted Gunning transceiver logic+) signal transmission and interface technology are analyzed in this paper. To resolve the problem on such short high-level duration time in traditional design, we have proposed an auxiliary charged circuit structure. According to what I have analyzed, we design and realize an AGTL+ interface circuit, which is completely compatible with Itanium 2 interface and has high-speed and high noise margin. The operating frequency of circuit reaches to 500MHz by SPICE simulation in the condition of 0.18mum standard CMOS process
Keywords
CMOS logic circuits; logic design; system buses; 0.18 micron; 500 MHz; AGTL+ output buffer; CMOS process; Itanium 2 interface; SPICE simulation; assisted Gunning transceiver logic+; auxiliary charged circuit; interface circuit; noise margin; signal transmission; Circuit simulation; Circuit synthesis; Frequency; Laboratories; Logic design; Microprocessors; Signal processing; Signal resolution; Transceivers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location
Shanghai
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611404
Filename
1611404
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