Study of the SEU Effect Mechanism on SOI PMOS by 2-D Simulation

2D device simulation with an ideal condition is used to study the mechanism for single-event upset (SEU) of SOI pMOS, which can be more significant in SRAM when gate length is scaling down. The mechanism can be associated with displacement current. Displacement currents across the box layer can be induced as charge is generated in the SOI substrate by an ion strike. It perturbs the electric fields in the substrate near the oxide/substrate interface, thus an abnormal current is observed in drain. The displacement current is related to the box layer thickness, the substrate doping species and concentration, also the drain area. Therefore all this parameter is critical in the design of SOI SRAM ICs