A novel slave-clock implementation approach for telecommunications network synchronisation

Network synchronisation has gained increasing attention since the introduction of the Synchronous Digital Hierarchy (SDH), as the network synchronisation performance has a major impact on the phase transfer characteristic of SDH-based networks. This is due to the SDH-internal bit rate adaptation technique. This paper discusses a new approach for the cost-efficient implementation of SDH Equipment Clocks (SEC), which are the basis for improved network synchronisation. The characteristics of the oscillator and the phase detector have a significant effect on the phase error generated by the clock. The paper proposes a synthesiser-based PLL structure employing a fixed frequency highly stable oscillator. A novel approach for an all-digital phase detector provides enhanced resolution, thereby reducing the phase error. Theoretical results obtained from analytical calculations and simulations are complemented by measurement results of a prototype clock to demonstrate the feasibility of this approach