A Robust Novel Technique for SPICE Simulation of ESD Snapback Characteristic

This paper presents a robust and novel technique for the circuit simulation of ESD (electrostatic discharge) snapback characteristic. A new linearization scheme for the avalanche current model in ESD evaluation shows a good convergence behavior during ESD stress simulation. This technique is compatible with the traditional circuit simulator based on the modified nodal analysis (MNA) like SPICE. We have implemented a simple ESD MOSFET model in SPICE3f5, and the simulation results are discussed