FPGA implementation of alterable parameters RSA public-key cryptographic coprocessor

This paper studies on the FPGA implementation of RSA public-key cryptographic coprocessor based on systolic array architecture, the typical Montgomery´s algorithm is presented first, in order to make it suitable for implementation on Altera´s FPGA, a modified radix-2 version is proposed and then a high-performance architecture is designed for modular multiplication. The conception of alterable parameter is applied in this design also, which extends the flexibility effectively. The proposed RSA coprocessor has distinctive features that not only computation speed is significantly fast but also hardware overhead is drastically decreased