Compact model of LDMOS for circuit simulation

Author

Ma, Yutao ; Chen, Ping ; Liang, Hancheng ; Ma, James ; Jeng, Min-Chie ; Liu, Zhihong

Author_Institution

Cadence Design Syst. Inc., San Jose, CA

fYear

2006

fDate

Oct. 2006

Firstpage

1380

Lastpage

1382

Abstract

A new compact LDMOS is introduced in this paper for circuit simulation. Features covered in this model relevant for a LDMOS device include: unique bias dependent drift region resistance model accounting for velocity saturation, bias dependent overlap region resistance model, dual Isub model to model Iii current in different region in the device and different biases, multiple junction modeling for parasitic diode, and gate/substrate resistance network for RF modeling as well as self-heating effects. The model is validated using different LDMOS technologies

Keywords

MOS integrated circuits; circuit simulation; integrated circuit modelling; LDMOS; RF modeling; circuit simulation; compact model; dual Isub model; gate/substrate resistance network; multiple junction modeling; parasitic diode; quasi-saturation; resistance model; self-heating effects; velocity saturation; CMOS technology; Capacitance; Circuit simulation; Diodes; Geometry; High power amplifiers; Radio frequency; Scalability; Solid modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306189

Filename

4098415