On-wafer BIST of a 200 Gb/s failed-bit search for 1 Gb DRAM

For giga-scale DRAM, it is important to reduce test time. Built-in self-test (BIST) for a 1 Gb DRAM realizes a 200 Gb/s failed-search for repair with redundancy and reduces on-wafer function test time to less than 1/100 that of a bit-by-bit test. An array architecture, with very-long word (VLW) transfer circuits, probes DRAM internal nodes and transfers a 4 kb pass or fail bit-map. An on-wafer test management unit (TMU), includes a failed-address aligner (FAA) that converts a transferred 4 kb VLW into two streams of l0 b/spl times/l6 w(word) failed-address data. Major BIST functions are continuous test vector generation and failed-bit detection. Line test widely known as a failed-bit detection method, reduces the final test time. However, line-test circuits are not adequate to search and identify failed-bits in DRAM wafer test. In this on-wafer BIST, if failed-bits are detected, the failed-addresses are directly sent to an external tester, shortening failed-bit search time to within the same order as line-test time. The DRAM and two TMUs (UP and DN) concurrently operate on a wafer. The TMUs are on both sides of the DRAM, partitioned by scribe lines.