DocumentCode :
3470397
Title :
A 170 mW 10 b 50 Msample/s CMOS ADC in 1 mm/sup 2/
Author :
Bult, K. ; Buchwald, A. ; Laskowski, J.
fYear :
1997
fDate :
8-8 Feb. 1997
Firstpage :
136
Lastpage :
137
Abstract :
This 10 b AD-converter at a sample rate of 5O MSample/s, embedded in 50mm/sup 2/ of digital circuitry, shows 8.7 effective bits. A straight flash-architecture would need 1023 accurate fast comparators. With a 2 V input range, a comparator offset voltage of no more than 1 mV can be tolerated. Taking into account that the 1 mV is a 3-6 sigma value, leads to a large chip. If, however, the signals to the comparator are amplified before the critical decision, simple small comparators would suffice. To cope with the dynamic offset caused by the clocking and latch action of the comparator itself, the architecture must tolerate comparator offsets of up to 60-80 mV. Hence, a gain of at least 30 is necessary. A single amplifier however, could not handle this, as the input range of 2 V would be amplified to 60 V. The approach here is to use a distributed amplifier.
Keywords :
CMOS integrated circuits; analogue-digital conversion; cascade networks; comparators (circuits)5602188; distributed amplifiers; interpolation; 10 bit; 170 mW; CMOS ADC; chip architecture; clocking; comparator; distributed amplifier; dynamic offset voltage; latching; sample rate; CMOS digital integrated circuits; Clocks; Distributed amplifiers; Impedance; Latches; Resistors; Strips; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
ISSN :
0193-6530
Print_ISBN :
0-7803-3721-2
Type :
conf
DOI :
10.1109/ISSCC.1997.585304
Filename :
585304
Link To Document :
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