• DocumentCode
    3470954
  • Title

    A Class of Hybrid LAPACK Algorithms for Multicore and GPU Architectures

  • Author

    Horton, M. ; Tomov, Stanimire ; Dongarra, Jack

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Univ. of Tennessee, Knoxville, TN, USA
  • fYear
    2011
  • fDate
    19-21 July 2011
  • Firstpage
    150
  • Lastpage
    158
  • Abstract
    Three out of the top four supercomputers in the November 2010 TOP500 list of the world´s most powerful supercomputers use NVIDIA GPUs to accelerate computations. Ninety-five systems from the list are using processors with six or more cores. Three-hundred-sixty-five systems use quad-core processor-based systems. Thirty-seven systems are using dual-core processors. The large-scale enabling of hybrid graphics processing unit (GPU)-based multicore platforms for computational science by developing fundamental numerical libraries (in particular, libraries in the area of dense linear algebra) for them has been underway for some time. We present a class of algorithms based largely on software infrastructures that have already been developed for homogeneous multicores and hybrid GPU-based computing. The algorithms extend what is currently available in the Matrix Algebra for GPU and Multicore Architectures (MAGMA) Library for performing Cholesky, QR, and LU factorizations using a single core or socket and a single GPU. The extensions occur in two areas. First, panels factored on the CPU using LAPACK are, instead, done in parallel using a highly optimized dynamic asynchronous scheduled algorithm on some number of CPU cores. Second, the remaining CPU cores are used to update the rightmost panels of the matrix in parallel.
  • Keywords
    computer graphic equipment; coprocessors; matrix algebra; multiprocessing systems; GPU architectures; graphics processing unit; hybrid LAPACK algorithms; matrix algebra; multicore architectures; quad-core processor-based systems; supercomputers; Dynamic scheduling; Graphics processing unit; Heuristic algorithms; Libraries; Multicore processing; Sockets; Cholesky; GPU; LU; QR; multicore;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Accelerators in High-Performance Computing (SAAHPC), 2011 Symposium on
  • Conference_Location
    Knoxville, TN
  • Print_ISBN
    978-1-4577-0635-6
  • Electronic_ISBN
    978-0-7695-4448-9
  • Type

    conf

  • DOI
    10.1109/SAAHPC.2011.18
  • Filename
    6031578