Title :
Design and modelling of a low phase noise pll frequency synthesizer
Author :
He, Xinhua ; Kong, Weixin ; Newcomb, Robert ; Peckerar, Martin
Author_Institution :
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD
Abstract :
This paper focuses on the low VCO sensitivity gain design, and modeling of a low phase noise 2.4GHz PLL frequency synthesizer. Tuning switch array is used in the LC tank to achieve low VCO gain and wide tuning rang simultaneously. The digital switch effects to phase noise have been analyzed in this paper. Moreover, a new method is provided for modeling and predicting phase noise of the frequency synthesizer. It overcomes the overall PLL noise analysis problem caused by large divider ratios. Simulation results show the synthesizer overall phase noise is -123.6dBc/Hz at 1MHz frequency offset. The PLL frequency synthesizer has been implemented in a standard 0.18mum CMOS technology
Keywords :
CMOS integrated circuits; UHF integrated circuits; UHF oscillators; circuit tuning; frequency synthesizers; integrated circuit design; phase locked loops; phase noise; voltage-controlled oscillators; 0.18 micron; 2.4 GHz; CMOS technology; LC tank; PLL noise analysis; digital switch effects; frequency synthesizer; low VCO sensitivity gain; low phase noise PLL; tuning switch array; CMOS technology; Frequency synthesizers; Phase locked loops; Phase noise; Predictive models; Semiconductor device modeling; Signal to noise ratio; Switches; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306314
