Title :
A 4.25 GHz BiCMOS clock recovery circuit with an AV-DSPD architecture for NRZ data stream
Author :
Nakamura, S. ; Tajima, A. ; Kinoshita, Y. ; Suemura, Y. ; Fukaishi, M. ; Suzuki, H. ; Itani, T. ; Miyamoto, H. ; Henmi, N. ; Yamazaki, T. ; Yotsuyanagi, M.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
Demand for high-speed serial data communication systems is increasing for computer data links using the 4.25Gb/s ANSI fiber-channel standard. A clock-recovery circuit (CRC) that extracts a clock signal from the transmitted data stream is essential for these systems. An AV-DSPD architecture operates at a frequency two times higher than that of an internal phase detector that limits the conventional CRC frequency. A CRC VCO is controlled by the absolute value of divided signal phase differences (AV-DSPD). Based on the AV-DSPD architecture, a 4.25GHz CRC is suitable for non return to zero (NRZ) data streams. Although the CRC consists of bipolar transistors, fabrication is in 0.251/spl mu/m BiCMOS allowing the CRC to be integrated with other digital blocks, such as a byte-lock detector, necessary for data link systems using the fiber-channel standard.
Keywords :
BiCMOS digital integrated circuits; clocks; data communication; optical communication equipment; optical fibre communication; 0.25 micron; 4.25 GHz; ANSI fiber-channel standard; AV-DSPD architecture; BiCMOS clock recovery circuit; NRZ data stream; VCO; byte-lock detector; clock signal; computer data links; digital blocks; divided signal phase differences; high-speed serial data communication systems; transmitted data stream; ANSI standards; BiCMOS integrated circuits; Clocks; Communication standards; Computer architecture; Cyclic redundancy check; Data communication; Data mining; Frequency; Optical fiber communication;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585374
