Title :
An 80 mm/sup 2/ MPEG2 audio/video decode LSI
Author :
Okada, Y. ; Nakamoto, T. ; Gunji, H. ; Hase, M. ; Oku, M. ; Tsuboi, Y. ; Mizosoe, H. ; Imazawa, K. ; Kudo, K. ; Hori, T. ; Saito, T. ; Hamano, T. ; Del Vecchio, P. ; Cismas, S.C. ; Monsen, K. ; Haber, Gadi ; Cruz-Rios, J. ; Ku, C. ; Malter, M. ; So, H. ;
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
This compact, single chip MPEG-2 audio/video decoder performs all necessary signal processing required for digital satellite TV and cable television (CATV) receivers based on the main profile at main level (MPEG-2 MP@ML) standard. This decoder uses 135,000 gates (2-input NAND equivalents) and occupies 8.6/spl times/9.3 mm/sup 2/ in a triple-layer-metal, 0.5 /spl mu/m CMOS standard-cell process and is much smaller than any MPEG-1/MPEG-2 decoder previously reported.
Keywords :
CMOS digital integrated circuits; audio signals; audio systems; decoding; digital signal processing chips; large scale integration; video coding; LSI; MPEG-2 MP@ML; cable television receiver; digital satellite TV receiver; signal processing; single chip audio/video decoder; triple-layer-metal CMOS standard-cell process; Bandwidth; Clocks; Decoding; Hardware; Large scale integration; Multimedia systems; Random access memory; Streaming media; Synchronization; Video signal processing;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585381
