Title :
A CAD compatible SOI/CMOS gate array having body-fixed partially-depleted transistors
Author :
Ueda, K. ; Nii, K. ; Wada, Y. ; Takimoto, I. ; Maeda, S. ; Iwamatsu, T. ; Yamaguchi, Y. ; Maegawa, S. ; Mashiko, K. ; Hamano, H.
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
Abstract :
This 0.35/spl mu/m 220kG SOI/CMOS gate array uses partially-depleted devices and allows use of cell libraries and design methods compatible with bulk/CMOS gate arrays by optimizing the basic-cell layout and power-line wiring. The SOI/CMOS gate array operates at 2.0V consuming 65% less power than typical 0.35/spl mu/m 3.3V bulk/CMOS gate arrays.
Keywords :
CMOS logic circuits; circuit layout CAD; logic CAD; logic arrays; silicon-on-insulator; 0.35 micron; 2.0 V; CAD compatible; SOI/CMOS gate array; basic-cell layout; body-fixed partially-depleted transistors; cell libraries; design methods; power-line wiring; Circuit testing; Delay effects; Delay estimation; Frequency estimation; Laboratories; Large scale integration; MOS devices; MOSFETs; Pulse width modulation inverters; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585386
