Title :
Low-Power CMOS Fully-Folding ADC with a Novel Bit Synchronization Architecture
Author :
Liu, Zhen ; Jia, Song ; Ji, Lijiu ; Zhang, Xing
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing
Abstract :
A 6-bit 250MHz low-power CMOS fully-folding analog-to-digital converter is designed in a 0.5mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one. A novel bit synchronization architecture also based on folding circuits is presented to reduce the number of comparators for bit synchronization and simplify the logic design. The total power dissipation is 34mW at a 5 V supply
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; synchronisation; 0.5 micron; 250 MHz; 34 mW; 5 V; 6 bit; bit synchronization architecture; comparators; digital CMOS process; folding circuits; logic design; low-power CMOS fully-folding ADC; low-power CMOS fully-folding analog-to-digital converter; Analog-digital conversion; Binary codes; CMOS process; Embedded system; Logic circuits; Logic design; Microelectronics; Power dissipation; Timing; Voltage;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306362
