A Low-Power 8-bit Folding A/D Converter with Improved Accuracy

In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction