Implementation of a Quasi-digital ADC on PLD

Author

Wang, Fu-yuan ; Li, Yong-liang ; Xi, Jiang-tao ; Chicharo, Joe F.

Author_Institution

Coll. of Inf. Eng., Zhengzhou Univ., Henan

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

1791

Lastpage

1793

Abstract

This paper presents a new way to implement stochastic logic-based analog-to-digit converters (ADCs) on a programmable logic device (PLD) chip. The proposed implementation is almost all digitalized so that the design can be done by using hardware description language and the results can be easily downloaded into a PLD chip. Both simulation and hardware test results are given

Keywords

analogue-digital conversion; circuit simulation; hardware description languages; programmable logic devices; PLD; circuit simulation; hardware description language; hardware test; programmable logic device; quasi-digital ADC; stochastic logic; Application specific integrated circuits; Australia; Digital circuits; Educational institutions; Fabrication; Logic; Low pass filters; Pulse circuits; Stochastic processes; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306449

Filename

4098545

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3472397