A 5 ns store barrier cache with dynamic prediction of load/store conflicts in superscalar processors

Many superscalar processors support out-of-order instruction execution and executes multiple instructions per cycle. One of the hazards of executing instructions out of order occurs when a prior instruction store is at the same memory location as a later instruction load, but the execution of the load occurs before the store is complete. Dynamic prediction about a store instruction involved in a load/store hazard can be used to delay a load instruction execution that is later in program order. The load/store conflict-prediction mechanism consists of a two-way set associative, 32-entry, two-ported SRAM cache used to contain information on store instructions involved in load/store conflicts.