Title :
An early-completion-detecting ALU for a 1 GHz 64 b datapath
Author :
Kondo, Y. ; Ikumi, N. ; Ueno, K. ; Mori, J. ; Hirano, M.
Author_Institution :
Syst. ULSI Eng. Lab., Toshiba Corp., Kanagawa, Japan
Abstract :
A technique with the advantages of pipelining and pseudo-asynchronous design is used to design a 1 GHz ALU datapath including a register file and bypass circuits. Cycle time is reduced from 1.5 ns to 1 ns. Transistor count is increased by only 23%.
Keywords :
digital arithmetic; logic design; 1 GHz; 1 ns; 64 bit; arithmetic logic unit; bypass circuit; cycle time; datapath; early-completion-detecting ALU; pipelining; pseudo-asynchronous design; register file; transistor count; Adders; Arithmetic; Clocks; Data engineering; Design engineering; Detectors; Latches; Logic circuits; Pipeline processing; Registers;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585466
