Low power dissipation in BIST schemes for modified Booth multipliers

Aiming at low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for modified Booth multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable test pattern generator (TPG) built of a 4-bit binary and a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. The achieved reduction of the total power dissipation is from 44.1% to 54.9%, the average reduction per test vector is from 21.4% to 36.5% while the reduction of the peaks is from 15.8% to 34.3%, depending on the implementation of the basic cells and the size of the MBM. The test application time is also reduced by 28.9% while the introduced BIST scheme implementation overhead is very small