Title :
Buffer Insertion Based on Single-pair Shortest-path Algorithm for Interconnect-Centric Floorplanning
Author :
Bai, Hong-Jie ; Dong, She-Qin ; Hong, Xian-Long
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
Abstract :
This paper studies the buffer insertion algorithm for interconnect centric floorplanning. We develop a buffer insertion algorithm based on single-pair shortest-path algorithm. With the assumption that buffers could be inserted anywhere in dead space, the authors construct a graph which takes geometry grid cells on borders of dead spaces as the vertex and reduce the buffer insertion problem into a shortest-path problem. With this algorithm applied, the number of nets which meet its timing constraint is improved
Keywords :
integrated circuit interconnections; integrated circuit layout; timing; buffer insertion; geometry grid cells; interconnect centric floorplanning; shortest-path algorithm; timing constraint; Computer science; Delay; Geometry; Routing; Runtime; Silicon; Space technology; Timing; Very large scale integration; Wire;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306493