An Improved ASIC/SOC Design Methodology for Quick Design Convergence

An improved ASIC/SOC design methodology for quick design convergence is described in this paper. Unlike the conventional ASIC/SOC design methodologies focused on automation, our new methodology focuses on streamlining the ASIC/SOC flow´s timing consuming steps by applying our expert´s BKM´s (best known methodology) to accelerate design convergence. It enabled us to shorten the time consuming phases dramatically with relatively minimal efforts. This resulted in smooth execution across different phases of the design and enabled us to meet the aggressive tape-out schedule