Low Power Decimation Filter Design for GSM Sigma-Delta A/D Converter Application

Author

Zhang, Chi ; Ofner, Erwin

Author_Institution

Carinthia Univ. of Appl. Sci., Villach

fYear

2006

fDate

2006

Firstpage

1886

Lastpage

1888

Abstract

A low power decimation filter design for GSM Sigma-Delta A/D converter application is proposed in this paper. The main power consumption CIC part is based on non-recursive structure that is an alternative to the standard CIC approach with a decimation factor of m-th power of two and m-th power of three. More research is done to find the break-even point of silicon area for non-recursive and recursive architecture of decimation filters with filter order 4. More than 70% of power can be saved for a filter with decimation factor 36 and filter order 4 by the non-recursive structure compared to the Hogenauer CIC architecture

Keywords

FIR filters; cellular radio; low-power electronics; sigma-delta modulation; CIC architecture; GSM; analogue-digital converter; cascaded-integrator-comb; decimation factor; decimation filter; sigma-delta converter; Band pass filters; Delta-sigma modulation; Digital filters; Energy consumption; Finite impulse response filter; Frequency; GSM; Power filters; Sampling methods; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306497

Filename

4098571