High Performance and Efficient Bandwidth Motion Compensation VLSI Design for H.264/AVC Decoder

This paper proposes advanced motion compensation VLSI architecture for H.264/AVC decoder system. In the paper, passive reuse and active reuse utilize memory bandwidth efficiently with 50% optimization compared with traditional design. Highly parallel cross filter style makes sub-pixel interpolation high throughput and low latency. Experiment and simulation results show that the architecture supports 30fps digital-HDTV (1280times720) clocking at 60MHz with 100MHz DRAM controller. Moreover, the architecture is modularized and easy to be integrated