High Performance and Efficient Bandwidth Motion Compensation VLSI Design for H.264/AVC Decoder

Author

Zhang, Nai-Ran ; Li, Mo ; Wu-chen Wu

Author_Institution

VLSI & Syst. Lab., Beijing Univ. of Technol.

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

1896

Lastpage

1898

Abstract

This paper proposes advanced motion compensation VLSI architecture for H.264/AVC decoder system. In the paper, passive reuse and active reuse utilize memory bandwidth efficiently with 50% optimization compared with traditional design. Highly parallel cross filter style makes sub-pixel interpolation high throughput and low latency. Experiment and simulation results show that the architecture supports 30fps digital-HDTV (1280times720) clocking at 60MHz with 100MHz DRAM controller. Moreover, the architecture is modularized and easy to be integrated

Keywords

DRAM chips; VLSI; high definition television; motion compensation; video codecs; video coding; 100 MHz; 60 MHz; AVC decoder; DRAM controller; H.264 decoder; VLSI design; digital-HDTV; memory bandwidth; motion compensation; sub-pixel interpolation; Automatic voltage control; Band pass filters; Bandwidth; Decoding; Delay; Design optimization; Interpolation; Motion compensation; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306500

Filename

4098574