DocumentCode
3474355
Title
Efficient reachability checking using sequential SAT
Author
Parthasarathy, G. ; Iyer, M.K. ; Cheng, K.-T. ; Wang, Li C.
Author_Institution
Dept. of ECE, California Univ., Santa Barbara, CA, USA
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
418
Lastpage
423
Abstract
Reachability checking and preimage computation are fundamental problems in ATPG and formal verification. Traditional sequential search techniques based on ATPG/SAT, or on OBDDS have diverging strengths and weaknesses. Here, we describe how structural analysis and conflict-based learning are combined in order to improve the efficiency of sequential search. We use conflict-based learning and illegal state learning across time-frames. We also address issues in efficiently bounding the search space in a single time-frame and across time-frames. We analyze each of these techniques experimentally and demonstrate the advantages of each technique. We compare performance against a commercial sequential ATPG engine and VIS [RK. Brayton et al., (1996)] on a set of standard benchmarks.
Keywords
automatic test pattern generation; computability; computational complexity; formal verification; logic testing; reachability analysis; search problems; sequential circuits; ATPG; conflict-based learning; formal verification; preimage computation; reachability checking; sequential SAT; sequential search technique; structural analysis; Automatic test pattern generation; Boolean functions; Data structures; Engines; Formal verification; Law; Legal factors; Runtime; Sequential circuits; State-space methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337611
Filename
1337611
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