Title :
Compact 12-port multi-bank register file test-chip in 0.35/spl mu/m CMOS for highly parallel processors
Author :
Sueyoshi, T. ; Uchida, H. ; Mattausch, H.J. ; Koide, T. ; Mitani, Y. ; Hironaka, T.
Author_Institution :
Hiroshima University
Abstract :
We designed a compact, high-speed, and low-power hank-type 12-port register file test chip for highly-parallel processors in 0.35μm CMOS technology. In this full-custom test chip design, 72% smaller area, 25% shorter access cycle time, and 62% lower power consumption are achieved in comparison to the conventional 12-port-cell-based register file.
Keywords :
CMOS process; CMOS technology; Chip scale packaging; Energy consumption; Processor scheduling; Registers; Surface-mount technology; System testing; Wiring; Yarn;
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location :
Yohohama, Japan
Print_ISBN :
0-7803-8175-0
DOI :
10.1109/ASPDAC.2004.1337644
