• DocumentCode
    3475152
  • Title

    FIFOs - Innovation Through Architecture

  • Author

    Sidman, Steven ; Spaderna, Dieter ; Miller, Jeffery ; Jenkins, David

  • Author_Institution
    Sharp Microelectronics Technology
  • fYear
    1991
  • fDate
    16-18 April 1991
  • Firstpage
    142
  • Lastpage
    143
  • Abstract
    Performance in SRAM based designs usually depends on applying a given process technology to a well known architecture. This is so because the key word in SRAM is random - the memory must meet its specifications for any pattern of accesses. FIFOs are a class of SRAM specialty memories with predictable patterns of address accesses. FIFO architectures which take advantage of this predictability permit faster parts, or parts with better speed/power trade-off in any given process than standard FIFO designs.
  • Keywords
    Boundary conditions; Circuits; Computer buffers; Interleaved codes; Microelectronics; Random access memory; Read-write memory; Technological innovation; Timing; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electro International, 1991
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ELECTR.1991.718189
  • Filename
    718189