Impact of Hot Carrier Degradation Modes on I/O nMOSFETS Aging Prediction

This work shows that channel hot carrier (CHC) in nMOSFET consists in two different regimes depending on the gate voltage (V_g). At low V_g, a simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions will be detailed. At high V_g, the second degradation mode becomes worse depending on V_d. This work focuses on the worst case degradation determination and the model effects on the device lifetime prediction in relation to the CHC degradation mechanisms. A combined and complementary use of charge pumping (CP) and direct current current voltage (DCIV) allows us to obtain the spatial interface traps (Nit) localization giving more information on Nit impact on linear transistor parameters degradation