Title :
Design of a four phase 25% duty cycle DLL with calibration
Author :
Ning Ning ; Yong Hu ; Jing Li ; Chang Yang ; Shuangyi Wu ; Qi Yu
Author_Institution :
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
This paper presents a design of a four phase 25% duty cycle of 400MHz DLL with calibration. To avoid the disadvantages of digital calibration method, it introduced an all-analog calibration method. Instead of DAC, CP is used in calibration loop to save power consumption and area occupying. With a 4 channel time-interleaved 6 bit flash ADC, the simulated results show that SNR is 30.8dB and 43.6dB with 800MHz input with and without calibration respectively.
Keywords :
analogue-digital conversion; calibration; digital-analogue conversion; power consumption; 4 channel time-interleaved flash ADC; CP; DAC; SNR; all-analog calibration method; calibration loop; digital calibration method; duty cycle DLL; frequency 400 MHz; power consumption; storage capacity 6 bit; Blogs; Calibration; Equations; Mathematical model; TV; CP; DLL; TI-ADC; calibration;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
Conference_Location :
Hong Kong
DOI :
10.1109/EDSSC.2013.6628088
