Title :
ESD Robustness of 40-V CMOS Devices With/Without Drift Implant
Author :
Chang, Wei-Jen ; Ker, Ming-Dou ; Lai, Tai-Hsiang ; Tang, Tien-Hao ; Su, Kuan-Cheng
Author_Institution :
Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu
fDate :
Oct. 16 2006-Sept. 19 2006
Abstract :
The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; ion implantation; power integrated circuits; 40 V; CMOS devices; ESD robustness; device structures; drain diffusion; drift implant; high-voltage MOSFET; layout parameters; layout spacing; CMOS process; CMOS technology; Electrostatic discharge; Implants; MOS devices; MOSFETs; Power system protection; Robustness; Testing; Voltage;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2006 IEEE International
Conference_Location :
South Lake Tahoe, CA
Print_ISBN :
1-4244-0296-4
Electronic_ISBN :
1930-8841
DOI :
10.1109/IRWS.2006.305237
