Evaluation of interface-states density for MOSFETs fabricated on high-index (114) silicon surfaces

Author

Molina, Juan ; Zuniga, Carlos ; Calleja, Wilfrido ; TORRES, ABEL ; Rosales, Pedro ; Gutierrez, Eladio ; Kendall, Don L.

Author_Institution

Electron. Dept., INAOE, Tonantzintla, Mexico

fYear

2013

fDate

3-5 June 2013

Firstpage

1

Lastpage

2

Abstract

Metal-oxide-semiconductor field-effect transistor (MOSFET) devices were fabricated on high-index silicon (114) surfaces and their threshold voltage (Vth) and interface-states density (Dit) parameters were both evaluated for the first time. Even though MOSFET devices aligned at 0°, 30°, 60° and 90° off the equivalent [110] direction present two closely related average Vth values, Dit evaluation shows that for all channel orientations (0°, 30°, 60° and 90°), this high-index silicon (114) surface develops a high-quality interface with SiO₂ in which few electrons are trapped so that Dit as low as 10¹⁰ cm^-2eV^-1 can be obtained.

Keywords

MOSFET; annealing; electron traps; interface states; silicon; silicon compounds; MOSFET; Si; SiO₂; channel orientations; electron traps; high-index silicon (114) surfaces; interface states density; metal-oxide-semiconductor field-effect transistor; threshold voltage; Atmospheric measurements; CMOS integrated circuits; Electron traps; Energy measurement; Logic gates; MOSFET circuits; Surface morphology; MOSFET; high-index silicon; interface states;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of

Conference_Location

Hong Kong

Type

conf

DOI

10.1109/EDSSC.2013.6628117

Filename

6628117