Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor

Scalability and customization properties of IP modules demand for new approaches in functional verification. We present a novel simulation-based solution for an Application-specific Instruction-set Processor (ASIP). Existing assembler code preselected by IP-configurable constraints forms the verification data base (reference stimuli). A behavioral “golden model” of the IP is used to derive expected responses suitable for any possible configuration of the final ASIP (RTL) implementation. Cycle-based verification is performed by stimulating the RTL model with the assembled reference stimuli and by comparing the outputs (actual responses) against the expected responses. Primary input stimulation is accomplished by reading back interface data prior written to a memory (model) under control of the reference stimuli. The synchronization of the configaration-dependent actual responses to the non-cycle-related expected responses is achieved by a mechanism based on “interface-specific activity scheduling”, which further more reduces the number of vectors efficiently, resulting in a significant simulation speed-up