120 V super junction LDMOS transistor

Super junction (SJ) is one of the emerging principles used in high-voltage high-power semiconductor devices. Implementation of SJ principle with charge balance in the pillars has overcome the “Silicon-limit”. SJ principle demands formation of back-to-back reverse biased p-n pillars. Main technology constraint is formation of narrow pillars with high aspect ratio and charge imbalance in these pillars. We propose a method to obtain high breakdown voltage in planar SJ-LDMOS by reducing the effect of charge imbalance at the drain end without reducing width of the pillars and no significant change in I_ON. The breakdown voltage of 120 V in a HV CMOS technology with tox of 13nm is achieved without ION degradation, as compared to 100 V conventional LDMOS device.