Design for testability: it is time to deliver it for Time-to-Market

Techniques are described that target extending usability of exiting scan-based DFT approaches for activities beyond IC component testing. In particular, the need for applying DFT to improve product Time-to-Market is described and justified. This need is evident from observations that a System on a Chip (SoC) design poses serious design verification challenges that may impact overall product success in ways that can not be compensated for by improving product quality. DFT features are described that that bring system-level diagnostics tools, such as the system Logic Analyzer and the Service Processor, to the IC level in order to facilitate post-silicon debug and verification. Finally, it is pointed out that much work remains to be done by existing EDA companies (or new entrepreneurial companies) to provide new tools that integrate the new DFT features into the SoC synthesis flow