Analysis and measurement of chip current imbalances caused by the structure of bus bars in an IGBT module

Author

Ohi, Takeshi ; Horiguchi, Takeshi ; Okuda, Tatsuya ; Kikunaga, Toshiyuki ; Matsumoto, Hideo

Author_Institution

R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan

Volume

3

fYear

1999

fDate

1999

Firstpage

1775

Abstract

Chip current imbalances caused by the structure of bus bars in an insulated gate bipolar transistor (IGBT) module were analyzed using the three-dimensional finite element method (3D-FEM). To confirm the results of the analysis we also measured the current of each parallel circuit using a test module. The results of the analysis were in good agreement with the experimental results. The 3D-FEM analysis was therefore used to design a new structure of bus bars in a module and the analysis results of the good current sharing was presented

Keywords

busbars; electric current measurement; finite element analysis; insulated gate bipolar transistors; modules; 3D-FEM; IGBT module; bus bars structure; chip current imbalances measurement; current sharing; insulated gate bipolar transistor module; parallel circuit; three-dimensional finite element method; Bars; Bonding; Circuit testing; Conductors; Current measurement; Finite element methods; Impedance; Insulated gate bipolar transistors; Semiconductor device measurement; Semiconductor diodes;

fLanguage

English

Publisher

ieee

Conference_Titel

Industry Applications Conference, 1999. Thirty-Fourth IAS Annual Meeting. Conference Record of the 1999 IEEE

Conference_Location

Phoenix, AZ

ISSN

0197-2618

Print_ISBN

0-7803-5589-X

Type

conf

DOI

10.1109/IAS.1999.805980

Filename

805980