Title :
Arithmetically sub-optimal floating point digital filters an architectural power perspective
Author :
Pillai, R.V.K. ; Al-Khalili, D. ; Al-Khalili, A.J.
Author_Institution :
Concordia Univ., Montreal, Que., Canada
Abstract :
In CMOS floating point hardware design, transition activity scaling of functional units, taking into account the limitations of machine arithmetic, offers promising results as far as architectural power optimization of these units is concerned. This work targets characterization of the architectural power implications of floating point adder cores of DSP data paths during implementation of arithmetically sub-optimal floating point digital filters. Instrumented digital filter programs that emulate a DSP multiply-accumulate unit form the core of our experimental platform. With a class of arithmetically sub-optimal band pass/stop filters having a normalized centre frequency of 0.5, the transition activity scaled triple data path floating point adder scheme offers a power reduction of better than 75%.
Keywords :
CMOS digital integrated circuits; adders; band-pass filters; band-stop filters; circuit optimisation; digital filters; floating point arithmetic; CMOS floating point hardware design; DSP data paths; adder scheme; architectural power perspective; arithmetically sub-optimal floating point digital filters; band-pass filters; band-stop filters; floating point adder cores; normalized centre frequency; power optimization; power reduction; transition activity scaling; Adders; Band pass filters; Design optimization; Digital filters; Digital signal processing; Energy consumption; Finite impulse response filter; Floating-point arithmetic; Frequency; Hardware;
Conference_Titel :
Electrical and Computer Engineering, 1999 IEEE Canadian Conference on
Conference_Location :
Edmonton, Alberta, Canada
Print_ISBN :
0-7803-5579-2
DOI :
10.1109/CCECE.1999.807265