Arithmetically sub-optimal floating point digital filters an architectural power perspective

In CMOS floating point hardware design, transition activity scaling of functional units, taking into account the limitations of machine arithmetic, offers promising results as far as architectural power optimization of these units is concerned. This work targets characterization of the architectural power implications of floating point adder cores of DSP data paths during implementation of arithmetically sub-optimal floating point digital filters. Instrumented digital filter programs that emulate a DSP multiply-accumulate unit form the core of our experimental platform. With a class of arithmetically sub-optimal band pass/stop filters having a normalized centre frequency of 0.5, the transition activity scaled triple data path floating point adder scheme offers a power reduction of better than 75%.