The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices

Author

Solinas, Marco ; Badia, R.M. ; Bodin, Francois ; Cohen, Asaf ; Evripidou, Paraskevas ; Faraboschi, Paolo ; Fechner, B. ; Gao, Guang R. ; Garbade, A. ; Girbal, Sylvain ; Goodman, D. ; Khan, Bilal ; Koliai, Souad ; Feng Li ; Lujan, Mikel ; Morin, L. ; Mende

Author_Institution

Dip. di Ing. dell´Inf., Univ. di Siena, Siena, Italy

fYear

2013

fDate

4-6 Sept. 2013

Firstpage

272

Lastpage

279

Abstract

Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper describes the project and provides an overview of the research carried out by the TERAFLUX consortium.

Keywords

data flow computing; mainframes; reliability; European Union; FET large-scale project; TERAFLUX consortium; TERAFLUX project; dataflow principles; extreme-scale systems; future and emerging technology large-scale project; manageable architecture design; next generation teradevices; programmability; reliability; semiconductor technologies; transistors; Computer architecture; Hardware; Instruction sets; Parallel processing; Programming; Reliability; Transistors; architecture; compilation; dataflow; exascale computing; many-cores; multi-cores; programming model; reliability; simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design (DSD), 2013 Euromicro Conference on

Conference_Location

Los Alamitos, CA

Type

conf

DOI

10.1109/DSD.2013.39

Filename

6628287