A systolic architecture for channel equalization based on a piecewise linear fuzzy logic algorithm

A systolic architecture dedicated to a piecewise linear fuzzy logic algorithm for a nonlinear channel equalization is presented. The piecewise linear membership function proposed for the inference step is more suitable for a VLSI implementation than the Gaussian function proposed in the literature. Depending on the number of piecewise linear membership functions (m) on the input space, the equalizer can perform for linear or nonlinear channel equalization. The performance evaluation of the systolic architecture is evaluated in terms of speed and area. The latency and throughput of the 16-bits design are respectively (2m+1)f/sub c/ and f/sub c/, where f/sub c/ is the clock frequency. In 0.5 /spl mu/m CMOS technology the f/sub c/ is evaluated at 40 MHz.