DocumentCode
3480247
Title
A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram
Author
Nambu, H. ; Kanetani, K. ; Idei, Y. ; Masuda, T. ; Higeta, K. ; Ohayashi, M. ; Usami, M. ; Yamaguchi, K. ; Kikuchi, T. ; Ikeda, T. ; Ohhata, K. ; Kusunoki, T. ; Homma, N.
Author_Institution
Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan
fYear
1994
fDate
9-11 June 1994
Firstpage
109
Lastpage
110
Keywords
BiCMOS integrated circuits; CMOS memory circuits; Decoding; Delay effects; Laboratories; Power dissipation; Pulse width modulation inverters; Random access memory; Read-write memory; Space vector pulse width modulation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-1918-4
Type
conf
DOI
10.1109/VLSIC.1994.586240
Filename
586240
Link To Document