DocumentCode
348125
Title
A framework for extracting defect density information for yield modeling from in-line defect inspection for real-time prediction of random defect limited yields
Author
Segal, Julie ; Gordon, Aaron ; Sajoto, Daan ; Duffy, Brian ; Kumar, Madan
Author_Institution
HPL Inc., San Jose, CA, USA
fYear
1999
fDate
1999
Firstpage
403
Lastpage
406
Abstract
This paper describes a technique for filtering optically measured in-line defect densities (DDmeas) in order to arrive at defect densities (DDreal) which can be combined with critical areas to predict single layer random defect limited yield. The technique involves correlating in-line defects with bitmap failures to establish the relationship between the optically measured defect density and the defect density required for critical area based yield modeling. That relationship, once established, applies to logic devices as well as memories. This procedure can predict single layer random defect limited yields on a real-time basis as lots are inspected
Keywords
digital integrated circuits; failure analysis; inspection; integrated circuit modelling; integrated circuit yield; bitmap failures; critical areas; defect density information; in-line defect inspection; optically measured in-line defect densities; random defect limited yields; real-time prediction; single layer random defect limited yields; yield modeling; Area measurement; Contacts; Data mining; Density measurement; Electrical fault detection; Inspection; Optical detectors; Predictive models; Random access memory; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1523-553X
Print_ISBN
0-7803-5403-6
Type
conf
DOI
10.1109/ISSM.1999.808821
Filename
808821
Link To Document