Partial SOI LDMOSFETs for high-side switching

Author

Lim, H.T. ; Udrea, F. ; Garner, D.M. ; Sheng, K. ; Milne, W.I.

Author_Institution

Dept. of Eng., Cambridge Univ., UK

Volume

1

fYear

1999

fDate

1999

Firstpage

149

Abstract

This paper describes the switching characteristics of Partial SOI LDMOSFET´s in high-side configuration based on the results of numerical simulations. The effects of the substrate bias on the on-state and output capacitances of a device on a Partial SOI substrate are discussed and compared to a conventional SOI substrate. It is shown that having the Partial SOI LDMOSFETs operating in source-high conditions will help to achieve a faster turn-off due to reduced parasitic capacitances. In addition, it is shown that the turn-off speed of Partial SOI LDMOSFETs is at least 3 times higher than of conventional SOI LDMOSFETs

Keywords

field effect transistor switches; power MOSFET; power semiconductor switches; silicon-on-insulator; high-side switching; numerical simulation; parasitic capacitance; partial SOI LDMOSFET; power device; specific on-resistance; substrate bias; turn-off characteristics; CMOS technology; Conductivity; Etching; Integrated circuit technology; Isolation technology; Numerical simulation; Parasitic capacitance; Power integrated circuits; Silicon on insulator technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 1999. CAS '99 Proceedings. 1999 International

Conference_Location

Sinaia

Print_ISBN

0-7803-5139-8

Type

conf

DOI

10.1109/SMICND.1999.810450

Filename

810450