DocumentCode
348238
Title
Optimal allocation of carry-save-adders in arithmetic optimization
Author
Junhyung Um ; Taewhan Kim ; Liu, C.L.
Author_Institution
Dept. of Comput. Sci. & Adv. Inf., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fYear
1999
fDate
7-11 Nov. 1999
Firstpage
410
Lastpage
413
Abstract
Carry-save-adder(CSA) is one of the most widely used schemes for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocation of CSAs. Specifically, we present a polynomial time algorithm which finds an optimal-timing CSA allocation for a given arithmetic expression. In addition, we extend our result for CSA allocation to the problem of optimizing arithmetic expressions across the boundary of design hierarchy by introducing a new concept, called auxiliary ports. Our algorithm can be used to carry out the CSA allocation step optimally and automatically, and this can be done within the context of a standard HDL synthesis environment.
Keywords
adders; carry logic; hardware description languages; logic design; optimisation; HDL synthesis environment; arithmetic expressions; arithmetic optimization; carry-save-adders; design hierarchy; optimal allocation; optimal-timing allocation; polynomial time algorithm; Adders; Algorithm design and analysis; Arithmetic; Circuit synthesis; Computer science; Delay; Design optimization; Information technology; Polynomials; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-5832-5
Type
conf
DOI
10.1109/ICCAD.1999.810685
Filename
810685
Link To Document